1. Field of the Invention
The present invention relates to a semiconductor device effectively used for a pixel switch or a drive circuit of an active-matrix display device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A conventional semiconductor device having an active layer made of silicon semiconductor such as amorphous silicon (to be referred to as a-Si:H hereinafter), micro-crystalline silicon, polycrystalline silicon (to be referred to as p-Si hereinafter), single crystalline silicon, or the like can be uniformly formed on an insulating surface with a relatively large area. For this reason, the semiconductor device is used for a pixel switch or a drive circuit of an active-matrix display device.
FIG. 1 is a schematic sectional view showing a general thin-film transistor (to be referred to as a TFT hereinafter) used as a pixel switch of an active-matrix display device. The TFT will be briefly described below with reference to FIG. 1.
A TFT 59 is mainly constituted by a transparent insulating substrate 10 such as a glass substrate or a quartz substrate, a gate electrode 13 formed on the transparent insulating substrate 10, a gate insulating film 11 formed on the gate electrode 13, a silicon semiconductor silicon thin film 23 made of a-Si:H, p-Si, or the like and formed on the gate electrode 13 through the gate insulating film 11, a channel protective film 33 formed on the silicon semiconductor thin film 23, source and drain electrodes 55 and 53 electrically connected to the silicon semiconductor thin film 23, and low-resistance semiconductor films 43 and 45 formed to obtain preferable ohmic contacts between the silicon semiconductor thin film 23 and the source electrode 55 and between the silicon semiconductor thin film 23 and the drain electrode 53.
Since parasitic capacitances such as a gate-source capacitance (Cgs) formed between the gate electrode 13 and the drain electrode 53 and a gate-drain capacitance (Cgd) formed between the gate electrode 13 and the drain electrode 53 adversely affects the operation of the TFT 59, it is known that especially the channel protective film 33 is formed to be self-aligned to the gate electrode 13. More specifically, a photoresist film is formed on the channel protective film 33, the photoresist film is subjected to back exposure from the transparent insulating substrate 10 side by using the gate electrode 13 as a mask, and the resultant photoresist film is developed to leave the photoresist film in only an area in which the channel protective film 33 is to be formed. The resultant structure is patterned using the photoresist as a mask to form the channel protective film 33. In this manner, since the channel protective film 33 is self-aligned to the gate electrode 13, a channel protective film 33 is formed between the gate electrode 13 and the source electrode 55 or the drain electrode 53. Therefore, the parasitic capacitances such as the gate-source capacitance (Cgs) or the gate-drain capacitance (Cgd) can be decreased in magnitude in a channel region.
In the TFT 59, a silicon nitride (SiN.sub.x) film or the like is generally used as the channel protective film 33. This is because the silicon nitride film does not adversely affect the interface between the silicon nitride film and the silicon semiconductor thin film 23 and can also be easily patterned.
However, the channel protective film constituted by the silicon nitride film does not have good adhesion to the photoresist film for patterning the channel protective film. For this reason, the resist film may peel from the channel protective film during manufacture, and the channel protective film 33 may not be preferably patterned. Therefore, the following adverse effects occur. That is, the gate-source capacitance (Cgs) or gate-drain capacitance (Cgd) of the TFT 59 increases in magnitude, or the gate-source capacitances (Cgs) or gate-drain capacitances (Cgd) of respective TFTs 59 vary.